System in package (SiP) combines a plurality of active components, passive components, micro-electromechanical systems (MEMS), optical components, and other components having different functions into one unit to form a system or a subsystem that is capable of providing multiple functions. SiP allows heterogeneous integration of integrated circuits (ICs), and appears to be a desired package integration technique. Compared to system on chip (SoC) package, SiP is relatively simple and demonstrates advantages of shorter design cycle, shorter time-to-market cycle, and lower cost. Therefore, SiP can be used for the implementation of more complex systems.
Compared to conventional SiP, the wafer-level packaging (WLP) is a package integration process that is completed based on wafers. The WLP demonstrates various advantages, such as greatly reducing the area size of the package structure, reducing the manufacturing costs, optimizing the electrical performance, supporting batch manufacturing, etc. These advantages demonstrated by the WLP can significantly reduce the workload and the requirements on equipment.
Given the significant advantages of the WLP, how to better implement WLP has always been a hot research topic in the industry. The disclosed methods and structures for wafer-level SiP are directed to improve the implementation of WLP.